Integrated circuit density continues to increase thereby requiring tighter (smaller) device-to-device spacing. In addition, MOS gate channel lengths are scaling down for both higher performance and greater packing density.
One of the primary methods utilized in achieving such scaling is to reduce the junction depth of the source/drain regions and increase the substrate or well background dopant concentration. However, the reduction of the source/drain depth and increase of the background well concentration will lead to more abrupt source/drains, and lead to lower breakdown voltage between the active area and well. In some circuits, this reduction of breakdown voltage is not acceptable. One way of increasing the breakdown voltage between the active area and substrate is to add a deeper implant into selected active areas to grade the junction.